There have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, radio frequency integrated circuits (RFIC), central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates in one chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, microprocessor, high-speed data transceiver, and the like).
In many integrated circuits, a phase-locked loop (PLL) frequency synthesizer generates many of the clock signals that drive the integrated circuit. Phase-locked loops (and delay-locked loops (DLLs)) are well known to those skilled in the art and have been extensively written about. The dynamic performance of the frequency synthesizer that generates clock signals depends on several parameters, including the natural frequency (Fn), the damping factor (DF), the crossover frequency (FO) and the ratio of the comparison frequency (Fc) to the crossover frequency. The performance of the frequency synthesizer also depends on the performance of the charge pump located in the PLL. The charge pump pulse timing jitter and pulse amplitude noise both contribute to synthesizer phase noise.
A common problem for a conventional PLL based on voltage-controlled oscillator (VCO) is the granularity with which the output frequency may be adjusted. Conventional PLLs contain a frequency divider (i.e., divide-by-N) block in the feedback loop. If the input frequency is F(in), then the output frequency is F(out)=N[F(in)]. However, N is typically an integer, so that increasing or decreasing N results in large increments or large decrements in the output frequency. A fractional N PLL may be implemented that changes in smaller increments. However, a fractional PLL requires complex circuitry and has a much slower response time.
Therefore, there is a need in the art for improved frequency synthesizers for use in generating reference frequency signals. In particular, there is a need in the art for a phase-locked loop (PLL) frequency synthesizer that can be finely tuned over a range of frequencies. More particularly, there is a need for a PLL frequency synthesizer that can be finely tuned and that has a fast response time.